1. Field of the Invention
The present invention relates generally to computer based systems that employ multiple clocks which potentially differ in frequency. More particularly, the present invention relates to a system and method for determining the ratio between the frequencies of a CPU clock and a clock used to control other hardware within a computer system.
2. Related Art
Conventional computer systems generally use one or more clocks of a single frequency to control operations performed by the central processing unit (CPU), and to control operations which occur external to the CPU. External operations involve accesses by the CPU (and other devices) to components that are external to the CPU, such as memory arrays, peripheral devices, and other integrated circuits. In systems which use a single clock frequency, the operating speed of the CPU is limited by the speed of the devices connected to it. This operating speed limitation can significantly impede performance, since modern CPUs can commonly operate at clock rates considerably higher than is tolerable by existing peripheral devices.
A solution to this problem has been to use a fast CPU clock to control the operations by the CPU, while using a slower "secondary clock" to control certain operations external to the CPU. For example, a system might use a 100 megahertz (MHz) clock to control operations internal to the CPU, and a 50 MHz secondary clock to control all accesses on a system bus which is connected to the CPU. One advantage of such a system is the ability to potentially operate the CPU at close to its maximum speed. Thus, CPU operations which are not limited by the speed of external devices can be executed more rapidly than would be possible if a single clock frequency were used. A second advantage is the ability to upgrade to a faster CPU without having to replace the entire computer system.
Systems have also been designed to allow the CPU to be set to operate at one of two or more fixed ratios between the two clock frequencies. For example, a CPU system might be designed so that the "clock frequency ratio," defined as the ratio between the CPU clock frequency and the secondary clock frequency, can be set at 1:1, 2:1, and 3:1. Such designs allow the CPU clock frequency to be selected according to the particular configuration of the computer system.
The difficulty in designing this type of system has been the complexity of the synchronization logic required to interface the CPU with the components which operate at the slower speed. Most systems to date, therefore, essentially avoid this problem by only using a single clock frequency ratio of C:1, where C is an integer. Since this limitation requires the CPU frequency to be an integer multiple of the secondary clock frequency, it often prevents the CPU from being clocked at a close to its maximum speed.
Existing systems which employ synchronization logic additionally have the disadvantage of requiring a special clock buffer to receive the secondary clock. This clock buffer resides on the chip performing the synchronization function, which is often the CPU chip.
What is needed, therefore, is a system which will enable a computer system to be switched between two or more fixed clock frequency ratios, including ratios which fall between C:1 (for two consecutive integers C). It is desirable to design this system such that complex synchronization logic is not required. Additionally, it is desirable to design the system without running the secondary clock to the chip containing the synchronization logic.